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How to use Perl in your SystemVerilog HDL Design Flow?
Anyone who designs with SystemVerilog HDL has probably grown tired of generating module instantiations in a hierarchical design, or creating a new top level or lower level SystemVerilog HDL module. I have generated a few Perl Scripts that will automatically generate the module instantiations, top level module, and lower level module for you. These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the script output will be printed in the current file. If you invoke them from within a DOS Command Window, then you will have to either cut and paste into your SystemVerilog HDL file or pipe the output to a new file. These files are hosted on GitHub at the link below: Below are the scripts:
The scripts above have been modified to use a Perl Module named SystemVerilogTools, which can be downloaded [here]. Simply unzip the file into a temporary directory, change directory to ./jwwebbopen-SystemVerilogTools-*/module/ and execute the following commands:
  1. perl Makefile.PL
  2. make
  3. make install
How to use svtools.pl?
This utility is a combination of sv_mod_top.pl, sv_mod_low.pl, sv_inst.pl, sv_tb.pl, and sv_ucf.pl. This script implements the following functions: 
        Usage: svtools.pl [-h] [-v] [-i|-t|-u|-a|-z] [-f ]

                -h              Print this help message.
                -v              Verbose: Print Debug Information.
                -i              Generate SystemVerilog HDL Instantiation.
                -t              Generate SystemVerilog HDL Test Bench.
                -u              Generate UCF file from SystemVerilog HDL file.
                -a              Generate new SystemVerilog HDL top-level module file from Template.
                -z              Generate new SystemVerilog HDL low-level module file from Template.
                -f        SystemVerilog HDL input file.

                Example of Module Instantiation:
                        svtools.pl -i -f sample.sv
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How to use sv_mod_top.pl?
This utility is intended to make creating new SystemVerilog HDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "new_module_name.sv" when you type the following command: 
        !! sv_mod_top.pl -a -f new_module_name.sv
The script will generate the empty SystemVerilog HDL template for you in the file "new_module_name.sv". Note: "new_module_name.sv" is the name of the new SystemVerilog HDL file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:
  1. Change directory to the desired directory
    • cd C:\design\new_module
    • If the directory "new_module" does not exist type: mkdir C:\design\new_module, before changing directory.
  2. Type the following: perl sv_mod_top.pl -a -f new_module_name.sv
  3. When the script is finished you will see the message: "The script has finished successfully! You can now use new_module_name.sv."
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How to use sv_mod_low.pl?
This utility is intended to make creating new SystemVerilog HDL modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "new_module_name.sv" when you type the following command: 
	!! sv_mod_low.pl -z -f new_module_name.sv
The script will generate the empty SystemVerilog HDL template for you in the file "new_module_name.sv". Note: "new_module_name.sv" is the name of the new SystemVerilog HDL file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style. You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:
  1. Change directory to the desired directory
    • cd C:\design\new_module
    • If the directory "new_module" does not exist type: mkdir C:\design\new_module, before changing directory.
  2. Type the following: perl sv_mod_top.pl -z -f new_module_name.sv
  3. When the script is finished you will see the message: "The script has finished successfully! You can now use new_module_name.sv."
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How to use sv_inst.pl?
This utility is intended to make instantiation in svilog easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. 
	!! sv_inst.pl -i -f adder.sv
The script will retrieve the module definition from the file you specify and provide the instantiation for you in the current file at the cursor position.
For instance, if adder.sv contains the following definition: 
        module adder (input wire a, 
                      input wire b, 
                      output reg sum, 
                      output reg carry);
Then this is what the script will insert in your editor for you: 
	adder adder (
		.a (a),
		.b (b),
		.sum (sum),
		.carry (carry) 
	        );
The keyword "module" must be left justified in the svilog file you are instantiating to work.
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How to use sv_tb.pl?
This utility is intended to make creating new SystemVerilog HDL Test Bench modules easier using a good editor, such as VI. As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to instantiate. This script will create a new text file called "tb_module_name.sv" when you type the following command: 
        !! sv_tb.pl -t -f module_name.sv
The script will generate the SystemVerilog HDL test bench template for you with the port contents of "module_name.sv". Note: "module_name.sv" is the name of the existing SystemVerilog HDL file, and "tb_module_name.sv" is the new test bench file.
The script will retrieve the module definition from the "module_name.sv" file you specify and provide the instantiation for you in the new "tb_module_name.sv" file.
The keyword "module" must be left justified in the svilog file you are instantiating to work.
You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:
  1. Change directory to the desired directory
    • cd C:\design\module
  2. Type the following: perl sv_tb.pl -t -f module_name.sv
  3. When the script is finished you will see the message: "The script has finished successfully! You can now use tb_new_module_name.sv."
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How to use sv_ucf.pl?

This utility is intended to make the creation of UCF files for Xilinx designs easier.
As long as you set the top line to correctly point to your perl binary, and place this script in a directory in your path, you can invoke it from VI. Simply use the !! command and call this script with the filename you wish to generate a UCF from. 
	!! sv_ucf -u -f adder.sv
The script will retrieve the input/inout/output definitions from the file you specify and reformat it into the UCF format. It will then write a new file called "adder.ucf", which contains the pin assignments. Below is an example of the UCF file contents: 
                                                                              
#*****************************************************************
#
# adder.ucf module
#
#*****************************************************************
#
# UC Davis Confidential Copyright © 2006 
#
#*****************************************************************
#
# created on:	12/10/04
# created by:	Jeremy W. Webb
# last edit on:	12/10/04
# last edit by:	Jeremy W. Webb
# revision:	001
# comments:	Generated.
#
# board name:		Second Consvter Board
# board number:		E4449-63104
# board revision:	A
# device mpn:		XC3S200-4VQ100C
# 
#******************************************************************
#
#--------------------------------------
# T I M I N G   C O N S T R A I N T S
#--------------------------------------
# N/A

#--------------------------------------
# P I N   A S S I G N M E N T S 
#--------------------------------------
NET "FPGA_10MHz" LOC = "" | IOSTANDARD = LVCMOS33;
NET "FPGA_INT_SWP" LOC = "" | IOSTANDARD = LVCMOS33;
NET "FPGA_ID"  LOC = "" | IOSTANDARD = LVCMOS33;
The pin numbers are left blank for you to fill in with the correct values.
You can either use VI or a DOS Command prompt to run this script. If you want to use a DOS Command prompt, then see the instructions below:
  1. Change directory to the desired directory
    • cd C:\design\
  2. Type the following: perl sv_ucf.pl -u -f module_name.sv
  3. When the script is finished you will see the message: "The script has finished successfully! You can now use module_name.ucf."
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Jeremy W. Webb

Last Modified: Wednesday, March 18, 2015 09:45:35 AM