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How to use Matlab to verify Verilog HDL DSP designs?
When designing DSP systems using Verilog HDL, verifying the functionality
of the design can be very tedious using the ordinary HDL simulators (i.e., ModelSim).
Using Verilog HDL's file I/O capabilities, the simulation results of important
nodes in the DSP system can be written into a MATLAB file for more
detailed analysis. The Verilog HDL code below shows how to generate
the MATLAB file:
module tb();
// I/Os:
wire [35:0] out;
reg [17:0] a, b;
reg clk;
// *** Local Integer Declarations ***
integer i_cnt;
integer m_file1; // File ID for Matlab File
// Instantiate UUT:
// dsp performs: out = a*b;
dsp uut (.clk (clk), .a (a), .b (b), .out (out));
// Generate clock:
always #1.65 clk <= ~clk;
// initial block
initial
begin
$timeformat(-9, 0, " ns", 8);
clk = 0;
a = 0;
b = 0;
i_cnt = 0;
@ (posedge clk);
m_file1=$fopen("sim_data.m");
$fdisplay(m_file1, "%%DSP Verilog HDL testbench results for Matlab Simulation.");
$fdisplay(m_file1, "%%This file contains the inputs of a and b, and the outputs out.");
$fwrite(m_file1, "\n");
$display("Capture 8192 samples of individual values for an 8192-point FFT.");
for (i_cnt=0;i_cnt<8192; i_cnt=i_cnt+1)
begin
a = i_cnt;
b = 1-i_cnt;
$fdisplay(m_file1,"a(%1.0d) = %1.0d;",i_cnt+1,$signed(a));
$fdisplay(m_file1,"b(%1.0d) = %1.0d;",i_cnt+1,$signed(b));
$fdisplay(m_file1,"out(%1.0d) = %1.0d;",i_cnt+1,$signed(out));
@ (posedge clk);
end
$fclose(m_file1);
$stop;
end
endmodule;
The Verilog HDL code generates a MATLAB file that contains the multiplier a, the
multiplicand b, and the product out. The values in the MATLAB file are
signed decimal values. The file can now be used in a MATLAB simulation.
Likewise, MATLAB can be used to generate a Verilog HDL file by using its file I/O capabilities.
The MATLAB code used to generate a Verilog HDL file is shown below:
% Generate impulse response stimulus vector for Verilog HDL simulation:
fid = fopen('stim.v','w');
fprintf(fid,'module stim (input wire [9:0] addr,\n');
fprintf(fid,' input wire clk,\n');
fprintf(fid,' input wire rst_n,\n');
fprintf(fid,' output wire [17:0] s_data);\n');
fprintf(fid,'\n\n');
fprintf(fid,'wire [17:0] data_rom [50:0];\n\n');
fprintf(fid,'assign data_rom[0] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_...
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f;\n',...
1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
data3 = zeros(1,100);
for k=1:15,
fprintf(fid,'assign data_rom[%1.0f] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_...
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_...
%1.0f%1.0f%1.0f%1.0f;\n',k,data3(k),data3(k),...
data3(k),data3(k),data3(k),data3(k),data3(k),...
data3(k),data3(k),data3(k),data3(k),data3(k),
data3(k),data3(k),data3(k),data3(k),data3(k),data3(k));
end
fprintf(fid,'assign data_rom[16] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_...
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f;\n',...
0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
for k=17:50,
fprintf(fid,'assign data_rom[%1.0f] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_...
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f;\n',k,data3(k),...
data3(k),data3(k),data3(k),data3(k),data3(k),data3(k),...
data3(k),data3(k),data3(k),data3(k),data3(k),data3(k),...
data3(k),data3(k),data3(k),data3(k),data3(k));
end
fprintf(fid,'\n\n');
fprintf(fid,'//always @ (posedge clk or negedge rst_n)\n');
fprintf(fid,'//begin\n');
fprintf(fid,'\t//if (!rst_n)\n');
fprintf(fid,'\t\t//s_data[17:0] <= 18''h00000;\n');
fprintf(fid,'\t//else\n');
fprintf(fid,'\t\t//s_data[17:0] <= data_rom[addr];\n');
fprintf(fid,'//end\n');
fprintf(fid,'\tassign s_data[17:0] = data_rom[addr];\n');
fprintf(fid,'\nendmodule\n');
fclose(fid);
The MATLAB code generates a Verilog HDL file that contains a ROM that contains two impulse
functions. This ROM can be used to simulate a FIR filter in ModelSim to verify that the filter
coefficients are output in the correct order and value. The Verilog HDL module can be instantiated
in the Verilog HDL test bench of the DUT.
Jeremy W. Webb
Last Modified: Wednesday, March 18, 2015 09:45:35 AM